Following high integration and miniaturization of semiconductor elements in recent years, there has been developed a semiconductor device using, as a wiring interlayer insulating film (hereinafter referred to as an interlayer insulating film), an insulating film having a permittivity lower than that of a conventional silicon oxide film. For example, there have been developed an interlayer insulating film obtained by substituting a part of oxygen atoms contained in a silicon oxide film by fluorine, hydrogen, or a chemical species containing carbon and hydrogen, such as a methyl group, and an interlayer insulating film obtained by forming fine pores in one of those films to achieve a reduction in permittivity. Particularly, the porous interlayer insulating film introducing the fine pores is quite effective for reducing the permittivity and thus can reduce the parasitic capacitance in multilayer wiring. In view of this, the multilayer wiring with porous interlayer insulating films introduced therein is expected to be widely applied to supercomputers and digital home appliances requiring high calculation speeds, mobile devices such as portable telephones requiring low power consumption, and so on.
FIG. 30 shows a multilayer wiring manufacturing method using porous interlayer insulating films according to a prior art. On a Cu wiring layer (not shown) formed in advance, a barrier insulating film 1 of SiCN or the like having diffusion barrier properties to Cu, a via interlayer insulating film 2, an etching stopper 3 of SiO2 or the like, a wiring interlayer insulating film 4, and a hard mask 5 of SiO2 or the like are stacked in the order named (FIG. 30, (a)). Then, as shown in FIG. 30, (b), dual-damascene trenches each comprising a wiring trench 6 and a via hole 7 are formed using photoresists and reactive etching. Dual-damascene trench forming methods include a via-first process in which a via is first formed and then a photoresist is coated over the formed via to thereby form a wiring trench and a trench-first process in which a wiring trench is first formed and then a photoresist is coated over the formed wiring trench to thereby form a via hole. Then, as shown in FIG. 30, (c), after etch-back of the barrier insulating film 1 at the bottom of the via holes 7, a barrier metal 10 of Ta/TaN or the like is deposited on the inner walls of the openings and the entire surface of the hard mask 5 and then a Cu film 11 is deposited thereon by an electrolytic plating method. The excess portions, deposited on the hard mask, of the barrier metal and the Cu film are removed and flattened by a CMP (Chemical Mechanical Polishing) process (FIG. 30, (d)).
With respect to the multilayer wiring structure using porous interlayer insulating films, various problems on the process and device reliability have been actualized and there have been many proposals for overcoming them.
For example, as shown in FIG. 31, with respect to the side wall of the porous interlayer insulating film 23 (the via interlayer insulating film 2 or the wiring interlayer insulating film 4) after the formation of the opening by the etching, the coating and adhesion of the barrier metal 10 are lowered due to the influence of exposed pore portions 19. This causes degradation of the device properties due to diffusion of water, various process gases, or Cu. For this problem, in Japanese Unexamined Patent Application Publication (JP-A) No. 2004-193326 (Patent Document 1), pores exposed on the side wall of a wiring trench after etching are blocked by nonporous polyarylether to improve the coating of a barrier metal, thereby suppressing diffusion of Cu into a porous interlayer insulating film. Similarly, in Japanese Unexamined Patent Application Publication (JP-A) No. 2001-85522 (Patent Document 2), an atomic group bulkier than a hydroxyl group is impregnated into pores exposed on the side wall of a porous interlayer insulating film after etching, thereby suppressing the flow of metal, water, or gas into the film through the pores.
Japanese Unexamined Patent Application Publication (JP-A) No. 2000-183052 (Patent Document 3) describes, as a technique for increasing the adhesion between an interlayer insulating film and an underlying substrate, a manufacturing method that applies a physical impact, i.e. reverse sputtering, to the lower-layer substrate for the interlayer insulating film to form dangling bonds on the surface of the underlying substrate, thereby improving the adhesion thereof to the interlayer insulating film formed thereon. Further, the Patent Document 3 describes, as an adhesion improving method, a method of inserting a silicon oxide film or a silicon nitride film as an adhesive layer between an interlayer insulating film and an underlying substrate.
Japanese Unexamined Patent Application Publication (JP-A) No. 2005-79307 (Patent Document 4) discloses a porous interlayer insulating film manufacturing method that bakes a coated film by irradiating an electron beam for the purpose of strengthening the porous interlayer insulating film. In the above Patent Document 4, a film strength (elastic modulus) of 15 GPa is achieved in a porous interlayer insulating film having a pore size of about 1.5 nm.